As a semiconductor device for processing large amounts of information at high speeds, an Emb (Embedded) DRAM configured by embedding a high-capacity DRAM and a high-speed logic integrated circuit in one chip is in practical use.
However, in response to a demand for annually accelerating the miniaturization of a semiconductor device, the following various problems become obvious in the Emb DRAM.
(1) The substrate concentration of a semiconductor substrate forming the semiconductor device is being increased, so as to maintain a high performance of a transistor against the shrinkage of a DRAM memory cell. As a result, a concentration change at a junction portion in a DRAM section is becoming steeper.
Accordingly, an electric field applied to the junction portion is becoming stronger, causing a difficulty in suppressing a leak from the junction portion to the order of ppm in a megabit-class DRAM. As a result, the data-retention characteristics (generally referred to as Tail characteristics) of the DRAM conventionally controllable with a margin are difficult to maintain, similarly to the conventional DRAM.
In the current situation, no effective measures against the above problem are found except increasing the capacitance of a capacitor with changes in generation.
(2) With the shrinkage of the DRAM cell, the contact area between a diffusion layer leading contact (leading electrode) and a diffusion layer becomes narrower to cause an increase in contact resistance at a rate of about 200% every generation. It is expected that the contact resistance will become several kiloohms in the next 0.1 μm generation, which resistance may be comparable to the on-state resistance of a memory cell transistor.
When the contact resistance becomes large, variations in the contact resistance have a great effect not only on the operation of the memory cell transistor, but also on the operation of the DRAM, especially the high-speed operation of the DRAM. Therefore, a higher positioning accuracy between the contact and the diffusion layer is required in a manufacturing process for the DRAM. Particularly, in the DRAM required to perform a high-speed operation, the improvement in the positioning accuracy is a matter of concern from the viewpoint of ensuring performance.
(3) Further, with the shrinkage of the DRAM cell, the interlayer insulation distance between a word line and a diffusion layer leading contact formed aside the word line is becoming smaller every year. For example, to ensure a dielectric voltage between the word line and the diffusion layer leading contact, the interlayer insulation distance between the word line and the diffusion layer leading contact is said to be 20 to 30 nm as a limited distance. However, if the trend toward shrinkage in the area of the DRAM cell continues as it is, the interlayer insulation distance between the word line and the diffusion layer leading contact will become less than the limited distance of 20 to 30 nm in the next 0.1 μm generation.
(4) Conventionally, a WSi/doped polysilicon polycide structure is adopted as the word line in the DRAM to relieve the problem of a signal delay. However, the aspect ratio of the word line has been increased with the recent miniaturization of the DRAM, and it has been difficult to make a sufficiently low resistance in a wiring structure of the word line for the purpose of suppressing the signal delay on the word line. Particularly, in the Emb DRAM required to perform a high-speed operation, this signal delay on the word line is a serious problem affecting the access time to the DRAM.
To cope with this problem, wiring having a salicide structure is in practical use for a decrease in resistance of a gate electrode (word line).
However, if a salicide structure is applied to the gate electrode (word line) of a DRAM cell, offset SiO2 cannot be used to cause a hindrance to the shrinkage of the DRAM cell. Further, to maintain the data retention characteristics, a process for preventing the formation of salicide in the diffusion layer of the DRAM is required. Accordingly, the use of the salicide structure for the gate electrode is difficult at present.
(5) Further, with the shrinkage of the DRAM, it is essential to form an opening with no margin in forming a memory node contact in the DRAM. Moreover, the distance between the contact opening and the word line is near a limited distance corresponding to a dielectric voltage, as in the case of the diffusion layer contact.
As a result, the contact diameter is reduced and a technique for efficiently suppressing an increase in resistance with the small contact diameter is therefore required.
(6) On the other hand, the improvement in performance of a transistor in a logic section is also remarkable. In particular, a P+ gate electrode doped with boron ions by ion implantation to suppress an off-state leak in a P-channel transistor has been generally used.
In activating the P+ gate electrode by heat treatment, there arises a problem of so-called “punch-through” in which the boron ions as impurities are diffused into the substrate. As a result, there are the serious problems of variations in characteristics of the P-channel transistor, depletion of the gate electrode, and degradation in gate dielectric performance.
Further, doped polysilicon widely used for the diffusion layer contact in the DRAM is a material absolutely required to be activated by heat treatment, and attention must be paid to matching in mixed mounting.
In the next 0.1 μm generation, it will be necessary to further reduce the thickness of a gate oxide film, and the techniques allowable in the present 0.18 μm generation may become inapplicable.
Accordingly, it is expected that a drastic improvement in the structure itself of the Emb DRAM will be necessary to maintain the trend toward the improvement of a chip's performance.
As an element structure capable of solving the six above-mentioned problems expected to become obvious in the next 0.1 μm generation Emb DRAM and also capable of maintaining the trend toward the improvement of a chip's performance, there has been proposed a DRAM cell using a trench gate MOS transistor, or trench access transistor (TAT) having such a structure that the word line in the DRAM section is buried in a “trench” formed in a substrate.
A semiconductor device including a conventional trench gate MOS transistor (MOSFET) will now be described with reference to FIG. 5. The semiconductor device shown is an Emb DRAM having a DRAM memory section and a logic section in combination, wherein the DRAM memory section is configured by a TAT DRAM cell. FIG. 5 is a sectional view showing the configuration of a transistor section in the TAT DRAM cell. The logic section in the semiconductor device is not shown in FIG. 5, and a description therefor will be omitted herein, because it is not directly pertinent to the present invention.
The transistor section 10 in the TAT DRAM cell is an N-channel transistor, which includes a gate electrode 18 buried through a gate insulating film 16 in a trench 14 formed in a semiconductor substrate, e.g., Si substrate 12, a diffusion layer 20 formed in a surface region of the substrate on the opposite sides of the trench 14, and a diffusion layer leading electrode 22 connected to the diffusion layer 20.
The configuration of the transistor section 10 in the TAT DRAM cell will be further described in detail with reference to FIG. 5.
As shown in FIG. 5, isolation regions 24, each having a depth of about 0.1 to 0.2 μm, are formed in the Si substrate 12 by STI (Shallow Trench Isolation), for example. The trenches 14, each having a depth of about 50 to 100 nm, are formed in the Si substrate 12 and the isolation regions 24. The word line (gate electrode) 18 is formed in each trench 14 through the gate insulating film 16.
A P-well 26 is provided in a region of the Si substrate 12 between the adjacent isolation regions 24, i.e., in a transistor forming region, and a channel diffusion layer 28 having a high concentration is formed in a region of the Si substrate 12 between the P-well 26 and each trench 14.
In contrast, the concentration in a region of the semiconductor substrate on the opposite sides of each trench 14 and in a surface region of the semiconductor substrate is near the substrate concentration, which is an extremely low concentration.
The upper surface of the word line (gate electrode) 18 is lower in level than the surface of the Si substrate 12 near the upper portion of each trench 14 by 30 to 50 nm, preferably 40 to 50 nm, so as to ensure a dielectric voltage between the word line 18 and the diffusion layer leading electrode 22.
In FIG. 5, reference numeral 18a denotes a tungsten/tungsten-nitride layer or cobalt/cobalt-silicide layer.
Further, the source/drain diffusion layer 20 is formed in the surface region of the semiconductor substrate near the upper portion of each trench 14.
It is preferable to relieve a field strength to the Si substrate 12, and the concentration in the diffusion layer 20 and in a junction portion of the semiconductor substrate region to the diffusion layer 20 is therefore set to a low concentration, thereby forming a junction at a low field strength.
The region of the Si substrate 12 below the diffusion layer 20 is doped with almost no ions, so that the concentration in this region is extremely low. Accordingly, the N-P junction in this structure is an ultragraded junction. The ultragraded junction relieves an electric field in applying a reverse bias, thereby allowing suppression of a junction leak about two orders of magnitude larger than usual, which leak occurs at defective bits on the order of ppm in a megabit-class DRAM. The data retention characteristics for such defective bits dominate the chip performance of the DRAM, and the technique for suppressing the junction leak will become important in maintaining the data retention characteristics for the next-generation DRAM.
As mentioned above, the gate electrode 18 is buried in the Si substrate 12 through the gate insulating film 16, and the diffusion layer 20 is formed in the surface region of the Si substrate 12. Accordingly, the channel is formed so as to pass through the region of the substrate below the bottom of each trench 14 within which the gate electrode 18 is formed.
Thus, the transistor section in the DRAM constitutes a trench gate MOSFET having such a structure that the channel is formed so as to extend around each trench 14, so that a long effective channel length can be ensured to thereby stabilize the transistor characteristics of a DRAM cell used by applying a back bias to exhibit remarkable short-channel effects.
A CVD SiO2 film 32 having a thickness of 20 to 40 nm is formed on the Si substrate 12 inclusive of the diffusion layer 20 except the inside of each trench 14. Further, an SiO2 film 34 as a sidewall protective wall for each trench 14 is formed on an upper portion of the sidewall of each trench 14 so as to extend to the upper surface of the SiO2 film 32. Further, an SiN cap layer 36 is formed on the SiO2 film 32, the SiO2 film 34, and the gate electrode 18.
An interlayer insulating film 38 is formed on the SiN cap layer 36, and the upper surface of the interlayer insulating film 38 is planarized.
The diffusion layer leading electrode 22 is formed like a plug so as to extend through the interlayer insulating film 38, the SiN cap layer 36, and the CVD SiO2 film 32 to the diffusion layer 20. The leading electrode 22 is formed of phosphorous-doped polysilicon.
The leading electrodes 22 are connected to a capacitor and a bit line (both not shown) according to design.
In such a trench gate MOSFET as mentioned above, the steeper the slope of a subthreshold current with respect to a gate voltage applied, the better the switching characteristics. In other words, as an S parameter (Swing) becomes smaller to result in a steeper slope of the subthreshold current in a MOSFET, the switching characteristics become better.
The S parameter is defined as a parameter when an output end and an input end of a MOSFET or the like as a subject of measurement are terminated at a characteristic impedance of 50 Ω.
The miniaturization of a MOSFET must be achieved not only by merely reducing the size, but also as suppressing any undesirable phenomena, such as short-channel effects and punch-through, which become remarkable in association with a reduction in size of a gate electrode.
To suppress these phenomena, various improvements have been made in such a trench gate MOSFET as shown in FIG. 5. In the trench gate MOSFET, the channel is formed around the trench 14 to thereby ensure a gate length along the depth of the trench 14, so that a high dielectric voltage between the gate and the drain can be designed.
However, in the conventional trench gate MOSFET, as mentioned above, the channel inversion is difficult at right-angled corner portions formed by the side walls and the bottom wall of the trench 14 at its bottom portion, causing a problem that the transistor characteristics, especially the switching characteristics, do not reach an expected level.
In this case, the S parameter shows an extremely high value near 128 [mV], for example, and the current drive capability Ids shows an extremely low value near 1.5×10−6, for example.
Accordingly, it is an object of the present invention to provide a trench gate semiconductor device which can improve the difficulty of channel inversion to thereby improve the switching characteristics as maintaining the effect of suppression of short-channel effects and the high dielectric voltage characteristic between the gate and the drain, both characteristics being the merits of a trench gate MOSFET. It is another object of the present invention to provide a fabrication method for such a trench gate semiconductor device.